module uart(clk,rst,Rx_pin_in,Rx_en,smg [7:0],dig [2:0],tx_data [7:0],Tx_pin_out);
input clk,rst;
input Rx_pin_in,Rx_en;
input [7:0] tx_data;
output [7:0] smg;
output [2:0] dig;
output Tx_pin_out;
wire bps_clk;
wire clk_out1;
wire h1_sig;
wire idle_sig;
wire end_sig;
wire [7:0] rx_data;
bps u1(clk,rst,bps_clk);
detect u2(clk,rst,Rx_pin_in,h1_sig);
div u3(clk,rst,clk_out1);
tx u4(clk,rst,Rx_en,tx_data,bps_clk,Tx_pin_out);
rx u5(clk,rst,h1_sig,Rx_pin_in,bps_clk,Rx_en,idle_sig,end_sig,rx_data);
smg u6(rst,clk_out1,rx_data,seg,dig,end_sig);
endmodule
